1. Technical Field
The present invention relates to ferroelectric memories.
2. Related Art
In recent years, ferroelectric memories (FeRAMs: Ferroelectric Random Access Memories) that use ferroelectric capacitors as data storage capacitors have been in the limelight. These ferroelectric memories are widely used as memories that are mounted on transponders of RFID (Radio Frequency Identification) systems.
Large parasitic capacitance is present on word lines and plate lines of ferroelectric memories, and in particular, larger capacitance is parasitic on the plate lines. For this reason, a technology to have plate lines corresponding to each single word line hierarchized into a plurality of local plate lines by using plate line selection signals is known.
However, such a technology entails a problem in that the circuit size becomes larger as the plate lines are hierarchized by using NAND circuits and inverter circuits.
Also, a variety of technologies concerning drive circuits for driving word lines and plate lines of ferroelectric memories is known.
However, the aforementioned technologies entail a problem in that a voltage to be supplied to the word lines may become lower than the power supply voltage VCC due to the influence of the threshold voltage of transistors. As the selection voltage of word lines becomes less than VCC, a failure occurs in writing a logical value “1” in a memory cell, and this leads to a larger problem, particularly when the power supply voltage is designed to supply a low voltage. JP-A-10-229171 and JP-A-2001-283583 are examples of related art.